// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  perf_stat_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  AIC_TOP
// Version       :  V110
// Date          :  2017/7/10
// Description   :  The description of Hi MINI project 
// Others        :  Generated automatically by nManager V4.2 
// History       :  AIC_TOP 2018/03/20 21:35:31 Create file
// ******************************************************************************

#ifndef __PERF_STAT_REG_OFFSET_FIELD_H__
#define __PERF_STAT_REG_OFFSET_FIELD_H__

#define PERF_STAT_APB_CLK_GATE_LEN    1
#define PERF_STAT_APB_CLK_GATE_OFFSET 0

#define PERF_STAT_CMD_START_LEN    1
#define PERF_STAT_CMD_START_OFFSET 0

#define PERF_STAT_SAMPLE_CNT_REG_LEN    16
#define PERF_STAT_SAMPLE_CNT_REG_OFFSET 0

#define PERF_STAT_SAMPLE_NUM_REG_LEN    32
#define PERF_STAT_SAMPLE_NUM_REG_OFFSET 0

#define PERF_STAT_SAMPLE_STOP_LEN    1
#define PERF_STAT_SAMPLE_STOP_OFFSET 0

#define PERF_STAT_REAL_PORT_NUM_LEN    2
#define PERF_STAT_REAL_PORT_NUM_OFFSET 0

#define PERF_STAT_AXI_ADDR_MODE_LEN    1
#define PERF_STAT_AXI_ADDR_MODE_OFFSET 0

#define PERF_STAT_SEQ_ADDR_LEN_LEN    32
#define PERF_STAT_SEQ_ADDR_LEN_OFFSET 0

#define PERF_STAT_STAT_RST_CNT_LEN    9
#define PERF_STAT_STAT_RST_CNT_OFFSET 0

#define PERF_STAT_DESC_ERROR_EN_LEN      1
#define PERF_STAT_DESC_ERROR_EN_OFFSET   3
#define PERF_STAT_DESC_INT_EN_LEN        1
#define PERF_STAT_DESC_INT_EN_OFFSET     2
#define PERF_STAT_OVERTIME_INT_EN_LEN    1
#define PERF_STAT_OVERTIME_INT_EN_OFFSET 1
#define PERF_STAT_SAMPLE_INT_EN_LEN      1
#define PERF_STAT_SAMPLE_INT_EN_OFFSET   0

#define PERF_STAT_DESC_ERROR_CLR_LEN      1
#define PERF_STAT_DESC_ERROR_CLR_OFFSET   3
#define PERF_STAT_DESC_INT_CLR_LEN        1
#define PERF_STAT_DESC_INT_CLR_OFFSET     2
#define PERF_STAT_OVERTIME_INT_CLR_LEN    1
#define PERF_STAT_OVERTIME_INT_CLR_OFFSET 1
#define PERF_STAT_SAMPLE_INT_CLR_LEN      1
#define PERF_STAT_SAMPLE_INT_CLR_OFFSET   0

#define PERF_STAT_DESC_RAW_ERROR_STAT_LEN    1
#define PERF_STAT_DESC_RAW_ERROR_STAT_OFFSET 3
#define PERF_STAT_DESC_RAW_INT_STAT_LEN      1
#define PERF_STAT_DESC_RAW_INT_STAT_OFFSET   2
#define PERF_STAT_OVERTIME_INT_STAT_LEN      1
#define PERF_STAT_OVERTIME_INT_STAT_OFFSET   1
#define PERF_STAT_SAMPLE_RAW_INT_STAT_LEN    1
#define PERF_STAT_SAMPLE_RAW_INT_STAT_OFFSET 0

#define PERF_STAT_DESC_MASK_ERROR_STAT_LEN      1
#define PERF_STAT_DESC_MASK_ERROR_STAT_OFFSET   3
#define PERF_STAT_DESC_MASK_INT_STAT_LEN        1
#define PERF_STAT_DESC_MASK_INT_STAT_OFFSET     2
#define PERF_STAT_OVERTIME_MASK_INT_STAT_LEN    1
#define PERF_STAT_OVERTIME_MASK_INT_STAT_OFFSET 1
#define PERF_STAT_SAMPLE_MASK_INT_STAT_LEN      1
#define PERF_STAT_SAMPLE_MASK_INT_STAT_OFFSET   0

#define PERF_STAT_ALL_SAMPLE_NUM_LEN    32
#define PERF_STAT_ALL_SAMPLE_NUM_OFFSET 0

#define PERF_STAT_OVERTIME_CFG_CNT_LEN    32
#define PERF_STAT_OVERTIME_CFG_CNT_OFFSET 0

#define PERF_STAT_DEBUG_FIFO_FULL_LEN    1
#define PERF_STAT_DEBUG_FIFO_FULL_OFFSET 0

#define PERF_STAT_DEBUG_MONITOR_LEN    2
#define PERF_STAT_DEBUG_MONITOR_OFFSET 0

#define PERF_STAT_MONITOR_RESET_LEN    1
#define PERF_STAT_MONITOR_RESET_OFFSET 0

















#define PERF_STAT_PDRST_TMO_CNT_CFG_LEN    8
#define PERF_STAT_PDRST_TMO_CNT_CFG_OFFSET 0

#define PERF_STAT_RS_ENABLE1_LEN    2
#define PERF_STAT_RS_ENABLE1_OFFSET 0

#define PERF_STAT_RS_ENABLE2_LEN    2
#define PERF_STAT_RS_ENABLE2_OFFSET 0

#define PERF_STAT_RS_ENABLE3_LEN    2
#define PERF_STAT_RS_ENABLE3_OFFSET 0

#define PERF_STAT_RS_ENABLE4_LEN    2
#define PERF_STAT_RS_ENABLE4_OFFSET 0

#define PERF_STAT_RS_ENABLE5_LEN    2
#define PERF_STAT_RS_ENABLE5_OFFSET 0

#define PERF_STAT_RS_ENABLE6_LEN    2
#define PERF_STAT_RS_ENABLE6_OFFSET 0

#define PERF_STAT_LATENCY_HIST_TH1_LEN      8
#define PERF_STAT_LATENCY_HIST_TH1_OFFSET   24
#define PERF_STAT_LATENCY_HIST_TH0_LEN      8
#define PERF_STAT_LATENCY_HIST_TH0_OFFSET   16
#define PERF_STAT_STAT_GO_LEN               1
#define PERF_STAT_STAT_GO_OFFSET            13
#define PERF_STAT_OTSD_STAT_EN_LEN          1
#define PERF_STAT_OTSD_STAT_EN_OFFSET       9
#define PERF_STAT_LATENCY_STAT_EN_LEN       1
#define PERF_STAT_LATENCY_STAT_EN_OFFSET    8
#define PERF_STAT_CFG_RW_SEL_LEN            2
#define PERF_STAT_CFG_RW_SEL_OFFSET         6
#define PERF_STAT_CFG_ADD_REGION_SEL_LEN    2
#define PERF_STAT_CFG_ADD_REGION_SEL_OFFSET 4
#define PERF_STAT_GLOBAL_EN_LEN             1
#define PERF_STAT_GLOBAL_EN_OFFSET          0

#define PERF_STAT_LATENCY_HIST_TH5_LEN    8
#define PERF_STAT_LATENCY_HIST_TH5_OFFSET 24
#define PERF_STAT_LATENCY_HIST_TH4_LEN    8
#define PERF_STAT_LATENCY_HIST_TH4_OFFSET 16
#define PERF_STAT_LATENCY_HIST_TH3_LEN    8
#define PERF_STAT_LATENCY_HIST_TH3_OFFSET 8
#define PERF_STAT_LATENCY_HIST_TH2_LEN    8
#define PERF_STAT_LATENCY_HIST_TH2_OFFSET 0

#define PERF_STAT_STAT_ALARM_CLR_LEN              1
#define PERF_STAT_STAT_ALARM_CLR_OFFSET           28
#define PERF_STAT_OTSD_STAT_ALARM_MODE4_LEN       2
#define PERF_STAT_OTSD_STAT_ALARM_MODE4_OFFSET    26
#define PERF_STAT_OTSD_STAT_ALARM_MODE3_LEN       2
#define PERF_STAT_OTSD_STAT_ALARM_MODE3_OFFSET    24
#define PERF_STAT_OTSD_STAT_ALARM_MODE2_LEN       2
#define PERF_STAT_OTSD_STAT_ALARM_MODE2_OFFSET    22
#define PERF_STAT_OTSD_STAT_ALARM_MODE1_LEN       2
#define PERF_STAT_OTSD_STAT_ALARM_MODE1_OFFSET    20
#define PERF_STAT_OTSD_STAT_ALARM_MODE0_LEN       2
#define PERF_STAT_OTSD_STAT_ALARM_MODE0_OFFSET    18
#define PERF_STAT_OTSD_STAT_ALARM_EN_LEN          1
#define PERF_STAT_OTSD_STAT_ALARM_EN_OFFSET       16
#define PERF_STAT_LATENCY_STAT_ALARM_MODE6_LEN    2
#define PERF_STAT_LATENCY_STAT_ALARM_MODE6_OFFSET 14
#define PERF_STAT_LATENCY_STAT_ALARM_MODE5_LEN    2
#define PERF_STAT_LATENCY_STAT_ALARM_MODE5_OFFSET 12
#define PERF_STAT_LATENCY_STAT_ALARM_MODE4_LEN    2
#define PERF_STAT_LATENCY_STAT_ALARM_MODE4_OFFSET 10
#define PERF_STAT_LATENCY_STAT_ALARM_MODE3_LEN    2
#define PERF_STAT_LATENCY_STAT_ALARM_MODE3_OFFSET 8
#define PERF_STAT_LATENCY_STAT_ALARM_MODE2_LEN    2
#define PERF_STAT_LATENCY_STAT_ALARM_MODE2_OFFSET 6
#define PERF_STAT_LATENCY_STAT_ALARM_MODE1_LEN    2
#define PERF_STAT_LATENCY_STAT_ALARM_MODE1_OFFSET 4
#define PERF_STAT_LATENCY_STAT_ALARM_MODE0_LEN    2
#define PERF_STAT_LATENCY_STAT_ALARM_MODE0_OFFSET 2
#define PERF_STAT_LATENCY_STAT_ALARM_EN_LEN       1
#define PERF_STAT_LATENCY_STAT_ALARM_EN_OFFSET    0

#define PERF_STAT_LATENCY_STAT_ALARM_MIN_LEN    32
#define PERF_STAT_LATENCY_STAT_ALARM_MIN_OFFSET 0

#define PERF_STAT_LATENCY_STAT_ALARM_MAX_LEN    32
#define PERF_STAT_LATENCY_STAT_ALARM_MAX_OFFSET 0

#define PERF_STAT_OTSD_STAT_ALARM_MIN_LEN    32
#define PERF_STAT_OTSD_STAT_ALARM_MIN_OFFSET 0

#define PERF_STAT_OTSD_STAT_ALARM_MAX_LEN    32
#define PERF_STAT_OTSD_STAT_ALARM_MAX_OFFSET 0

#define PERF_STAT_OTSD_STAT_ALARM_STATUS_LEN       1
#define PERF_STAT_OTSD_STAT_ALARM_STATUS_OFFSET    1
#define PERF_STAT_LATENCY_STAT_ALARM_STATUS_LEN    1
#define PERF_STAT_LATENCY_STAT_ALARM_STATUS_OFFSET 0

#define PERF_STAT_LATENCY_STAT_COUNTER1_LEN    16
#define PERF_STAT_LATENCY_STAT_COUNTER1_OFFSET 16
#define PERF_STAT_LATENCY_STAT_COUNTER0_LEN    16
#define PERF_STAT_LATENCY_STAT_COUNTER0_OFFSET 0

#define PERF_STAT_LATENCY_STAT_COUNTER3_LEN    16
#define PERF_STAT_LATENCY_STAT_COUNTER3_OFFSET 16
#define PERF_STAT_LATENCY_STAT_COUNTER2_LEN    16
#define PERF_STAT_LATENCY_STAT_COUNTER2_OFFSET 0

#define PERF_STAT_LATENCY_STAT_COUNTER5_LEN    16
#define PERF_STAT_LATENCY_STAT_COUNTER5_OFFSET 16
#define PERF_STAT_LATENCY_STAT_COUNTER4_LEN    16
#define PERF_STAT_LATENCY_STAT_COUNTER4_OFFSET 0

#define PERF_STAT_OTSD_STAT_COUNTER0_LEN       16
#define PERF_STAT_OTSD_STAT_COUNTER0_OFFSET    16
#define PERF_STAT_LATENCY_STAT_COUNTER6_LEN    16
#define PERF_STAT_LATENCY_STAT_COUNTER6_OFFSET 0

#define PERF_STAT_OTSD_STAT_COUNTER2_LEN    16
#define PERF_STAT_OTSD_STAT_COUNTER2_OFFSET 16
#define PERF_STAT_OTSD_STAT_COUNTER1_LEN    16
#define PERF_STAT_OTSD_STAT_COUNTER1_OFFSET 0

#define PERF_STAT_OTSD_STAT_COUNTER4_LEN    16
#define PERF_STAT_OTSD_STAT_COUNTER4_OFFSET 16
#define PERF_STAT_OTSD_STAT_COUNTER3_LEN    16
#define PERF_STAT_OTSD_STAT_COUNTER3_OFFSET 0

#define PERF_STAT_OTSD_HIST_TH3_LEN    8
#define PERF_STAT_OTSD_HIST_TH3_OFFSET 24
#define PERF_STAT_OTSD_HIST_TH2_LEN    8
#define PERF_STAT_OTSD_HIST_TH2_OFFSET 16
#define PERF_STAT_OTSD_HIST_TH1_LEN    8
#define PERF_STAT_OTSD_HIST_TH1_OFFSET 8
#define PERF_STAT_OTSD_HIST_TH0_LEN    8
#define PERF_STAT_OTSD_HIST_TH0_OFFSET 0

#define PERF_STAT_L0C_STAT_CTRL_LEN    2
#define PERF_STAT_L0C_STAT_CTRL_OFFSET 0

#endif // __PERF_STAT_REG_OFFSET_FIELD_H__
